1. Field of the Invention
The present invention is related to a method of forming a CMOS transistor.
2. Description of the Prior Art
In general, a MOS transistor includes a substrate such as a silicon substrate, a source region, a drain region, a channel region positioned between the source region and the drain region, a gate positioned on the channel, a gate dielectric layer positioned between the gate and the substrate and a spacer positioned on the sidewall of the gate and the gate dielectric layer. When a MOS transistor is under a fixed electric field, the current passing through the channel region is proportional to the carrier mobility. Therefore, it would be desirable to implement the carrier mobility to optimize the performance of the MOS transistor.
One conventional approach for enhancing the carrier mobility is to form mechanical stresses within the channel region. For example, a compressive strained channel can be formed by epitaxially growing a SiGe (silicon germanium) layer on the substrate. In this way, the hole mobility is enhanced greatly. In another example, a tensilely stressed channel can be formed by epitaxially growing silicon directly over a SiGe layer. In this way, the electron mobility is enhanced.
The above-mentioned approaches are performed by utilizing the fact that silicon and germanium have a different lattice constant. In this way, band structure of the silicon is deformed because the lattice constant of germanium is greater than silicon. The carrier mobility is thereby increased and the performance of the MOS transistor is improved.
As the integrity of semiconductor devices increases, however, the size of the CMOS is decreasing. The demand for high speed CMOS is increasing as well. The conventional method of forming mechanical stresses within the channel region is no longer sufficient.